Integrated circuit designers have an array of modem tools, such as schematic entry programs and various descriptive languages, e.g., Verilog and VHDL (Very High-Level Descriptive Language), to facilitate the creation of various logic designs. Once a particular logic design is initially created, a designer may wish to compile the logic design to remove various errors. For example, compiling a VHDL file may reveal any of (1) minor syntax errors, (2) potential problems, i.e., warnings, that may or may not be of consequence and (3) major design errors of functional consequence. Typically, a designer can modify the entry file of a logic design until a compiler indicates that all design errors are apparently removed and any residual warnings are either removed or otherwise deemed harmless by the designer. The resulting compiled design can then be considered a model of the logic design.
Once a logic design is compiled, the integrated circuit designer may then wish to “realize” the resulting logic model. That is, a designer may wish to perform a number of operations on the logic model to convert the logic model from abstract mathematical and functional relationships to a more low-level form consisting of a description of various logic circuits and interconnecting pins, eg a gate level Verilog netlist.
Once the logic model is realized, the integrated circuit designer may wish to verify the functionality of the realized logic design. Conventional verification approaches include applying a “wrapper” to the realized logic design and then performing a simulation on the wrapped realized logic design. A wrapper is a software construct that enables a designer to interact with a logic design on a pin (nodal) level, i.e., feed simulated electrical signals to the realized logic design and/or estimate/measure the resulting signals produced by the realized logic design.
Unfortunately, verification techniques based on simulations of wrapped logic designs can require large amounts of computer processing power and memory. To complicate this issue, it should be appreciated that modern day integrated circuits have dramatically increased in size and capacity. That is, modern electronic technology has made it possible to put large numbers of increasingly complex electronic circuits on practicable-sized silicon dies. As a result, verifying such large logic designs can require impracticable amounts of computer resources. Accordingly, new systems and techniques directed to logic design and verification are desirable.